1. Field of the Invention
The invention relates to a method for fabricating a semiconductor structure, and more particularly, to a method of trimming hard mask for forming a gate electrode layer of a MOS structure.
2. Description of the Prior Art
During the process of manufacturing metal oxide semiconductor transistors (MOS transistors), the formation of a conductive gate plays an important role. In order to meet the demand of miniaturization of the semiconductor industry, the current channel length under the gate must meet the standard of less than 35 nm. To meet the less than 35 nm channel length requirement, it is crucial to control the critical dimension (CD) during the process of exposure of the gate so as to control the line width of the conductive layer (poly-Si layer for example) after the etching process. Because the current lithographic tool techniques are incapable of obtaining the ideal CD, trimming methods are employed in some prior art methods to reduce the size of gate line width. However, most photo resist layers useful in the current gate exposure process are 193 nm photo resist layers which are intrinsically less resistant to the etching condition than 365 nm photo resist layers are on account of acrylic and cycloalkenyl polymer composition in contrast to 365 nm photo resist layers composed of aryl moiety. Furthermore, the thickness of 193 nm photo resist layers reduces as the exposure wavelength shortens. Under the dual disadvantages of poor etching resistance and less and less thickness, it is hard for 193 nm photo resist layers to meet the minimum requirement of 30 nm owing to the available thickness being 10 nm or less during the trimming process on 193 nm photo resist layers.
In order to overcome the problem, the current techniques deals with the problems by transferring the pattern on the photo resist layer to the hard mask beneath the photo resist layer. After being patterned, the hard mask is ready for the trimming process to reduce the gate line width. In addition, the hard mask must have high etching selectivity to the conductive layer used in forming gate layer. Accordingly, the trimmed hard mask is ready to be the template for etching transfer process to define the line width of gate layer.
However, as only one trimming process is typically employed on the photo resist layer and the hard mask above the designated gate layer, issues such as line twisting or line less often occur on the hard mask beneath the photo resist layer and result in a flawed gate structure. Moreover, the hard mask is also prone to line collapse during the trimming procedure and the following etching on conductive layer, which would destroy the entire process or the results. Accordingly, it is important to develop a better method for trimming hard masks to form the gate of MOS transistors with ideal gate length.